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RTL - keyword
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items found: 2
1.
Comprehensive Abstraction of VHDL RTL Cores to ESL SystemC. Register-siirde taseme VHDL kirjelduste kompleksne abstraheerimine süsteemitaseme SystemC mudeliteks
Syed, Saif Abrar
20.04.2016
dissertations
2.
Hardware Modeling for Design Verification and Debug. Riistvara modelleerimine disaini verifitseerimise ja silumise jaoks
Tšepurov, Anton
14.06.2013
dissertations
items found: 2
1