title
Digitaalskeemide testitavuse analüüs struktuurselt sünteesitud otsustusdiagrammide abil
Testability analysis of digital circuits using the model of structurally synthesized BDDs
author
Adeniyi Olanrewaju, Adekoya
keywords
magistritööd
combinational circuits
signal probabilities
probabilistic controllability calculation
fault redundancy
structurally synthesized BDDs
master's theses
supervisor
Ubar, Raimund-Johannes
Oyeniran, Adeboye Stephen
defence date
06.06.2019
language
eng
institution
Tallinna Tehnikaülikool
Tallinn University of Technology
faculty
Infotehnoloogia teaduskond
School of Information Technologies
department / college
Arvutisüsteemide instituut
Department of Computer Systems