Toggle navigation
Search
Collections
Indexes
FAQ
Digikogu
Search
Collections
Indexes
FAQ
Intranet
Logi sisse
title
Kahefaasiline lineaarse keerukusega lagoritm rikete kollapseerimiseks digitaalskeemides
Double phase fault collapsing with linear complexity in digital circuit
author
Oyeniran, Adeboye Stephen
keywords
SSBDD
VLSI
magistritööd
fault collpasing
SSBDD
circuit testing
test generation
VLSI
master's theses
supervisor
Ubar, Raimund-Johannes
defence date
11.06.2015
language
eng
institution
Tallinna Tehnikaülikool
Tallinn University of Technology
faculty
Infotehnoloogia teaduskond
Faculty of Information Technology
department / college
Arvutitehnika instituut
Department of Computer Engineering
subunit
Arvutisüsteemide diagnostika ja verifitseerimise õppetool
Chair of Computer Systems Test and Verification
Download fulltext
pdf
1,38 MB