title
Area Efficient Design and Implementation of a Novel Divider Circuit Block
Uudne efektiivne jagamistehte riistvaraline realisatsioon
author
Patankar, Udayan Sunil
keywords
VLSI
FPGA
divider
restoring
non-restoring
digit recurrence
USP-Awadhoot divider
Awadhoot matrix
variable latency
dissertations
integraallülitused
algoritmid
jagamine
kompuutersimulatsioon
dissertatsioonid
description
Citation: Patankar, U. S. (2025). Area Efficient Design and Implementation of a Novel Divider Circuit Block [TalTech Press]. https://doi.org/10.23658/taltech.29/2025
serial number
29/2025
publisher
TalTech Press
TalTech Kirjastus
supervisor
Koel, Ants
Pardy, Tamás
defence date
28.05.2025
identifier
https://digikogu.taltech.ee/et/Item/bada7a0d-f54f-48bb-844d-37e23ad8d029
ISBN 978-9916-80-298-4 (PDF)
https://doi.org/10.23658/taltech.29/2025
language
eng
rights
CC BY-NC-SA
institution
Tallinn University of Technology
Tallinna Tehnikaülikool
faculty
School of Information Technologies
Infotehnoloogia teaduskond
department / college
Thomas Johann Seebeck Department of Electronics
Thomas Johann Seebecki elektroonikainstituut